The present invention relates generally to integrated circuit memory devices and, more particularly, to a single-clock dynamic compare circuit.
Set associative cache in high performance computer systems is bound by two critical paths, in terms of the time required to access the cache: (1) the cache array access and (2) the hit logic path, which refers to the path that determines whether or not the memory address resides in the cache. For a read operation, in order to speed up the cache access, the hit logic operation and the cache array read operation are typically overlapped in times. That is, both operations are performed in parallel during the same clock cycle.
As will also be appreciated by those skilled in the art, in a set associative cache, a tag memory stores at each addressable tag memory location the addresses of two or more (depending on the size of cache) blocks from main memory stored in the cache. A memory request address includes the cache tag memory address where the address of the requested data will reside in cache if it is in the cache. The addresses in the tag memory at that location are read out of the tag memory and compared with the memory request address. Both static comparators and dynamic comparators have been proposed in the art for comparing the tag address with the requested address in set associative cache memories. However, the implementation of a fully static compare path is generally slow in performance. On the other hand, the implementation of a fully dynamic compare path is complex both in circuit design and timing.